" Vim syntax file
" Language:	Verilog
" Maintainer:	Lai Han
" Last Update:  March 9th, 2009

" A bunch of useful Verilog keywords
" put this file to vim/syntax directory to overflow the default verilog syntax file

setlocal iskeyword+=`,$,_

syntax cluster Vsymbols contains=VerilogArithSynbol,VerilogSymbol,VerilogNumber,verilogOperator

syntax keyword VerilogReservedWords buf bufif0 bufif1 case casex casez coms default defparam disable
syntax keyword VerilogReservedWords edge else endcase endprimitive endspecify endtable event
syntax keyword VerilogReservedWords for forever highz0 highz1 if large library macromodule medium
syntax keyword VerilogReservedWords negedge nmos notif0 notif1 pmos posedge primitive pull0 pull1 pullup pulldown
syntax keyword VerilogReservedWords rcoms repeat rnmos rpmos rtran rtranif0 rtrainif1
syntax keyword VerilogReservedWords scalared small specify specparam strenth strong0 strong1 supply0 supply1
syntax keyword VerilogReservedWords table tran tranif0 tranif1
syntax keyword VerilogReservedWords vectored wait weak0 weak1 while wand wor

syntax keyword VerilogSystemTasks   $bitstoreal $countdrivers $display $fclose $fdisplay $finish
syntax keyword VerilogSystemTasks   $fmonitor $fopen $fstrobe $fwrite $finish $getpattern
syntax keyword VerilogSystemTasks   $history $hold $incsave $input $itor $key $list $log
syntax keyword VerilogSystemTasks   $monitor $monitoroff $monitoron $nokey $nolog $period $printtimescale
syntax keyword VerilogSystemTasks   $random $readmemb $readmemh $realtime $realtobits $recovery $reset
syntax keyword VerilogSystemTasks   $reset_count $reset_value $restart $rtoi $savle $scale $scope $setup
syntax keyword VerilogSystemTasks   $setuphold $showscopes $showvariable $shwvars $sreadmemb $screadmemh
syntax keyword VerilogSystemTasks   $stime $stop $strobe $time $timeformat $width $write

syntax keyword VerilogBlockSentence begin end fork join

syntax keyword VerilogPrecompile    parameter
syntax keyword VerilogPrecompile    `accelerate `autoexepand_vectors `celldefine `default_nettype `define
syntax keyword VerilogPrecompile    `else `endcelldefine `endif `endprotect `endprotected `expand_vectornets
syntax keyword VerilogPrecompile    `ifdef `ifndef `include `noaccelerate `noexpand_vectornets `noremove_gatenames
syntax keyword VerilogPrecompile    `noremove_netnames `nounconnected_drive `protect `protected
syntax keyword VerilogPrecompile    `remove_gatenames `resetall `timescale `unconnect_drive `undef `uselib

syntax keyword VerilogDataType      integer input inout output real reg wire
syntax keyword VerilogDataType      supply0 supply1 time tri tri0 tri1 triand trior trireg wand wor 

syntax keyword VerilogProcedure     always assign deassgin endmodule endfunction endtask force function
syntax keyword VerilogProcedure     initial module release task

syntax keyword VerilogArithSynbol   and nand nor not or xnor xor
syntax match   verilogOperator      "[&|~><!*#%@+/=?:.\^\-]"

syntax match   VerilogSymbol        "[,;()\[\]{}]"

syntax match   VerilogNumber        "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>"
syntax match   VerilogNumber        "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>"
syntax match   VerilogNumber        "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>"
syntax match   VerilogNumber        "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>"
syntax match   VerilogNumber        "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>"

syntax match   VerilogTimeScale     "[0-9]\+[munpf]\?s"

syntax region  VerilogComment       start="/\*" end="\*/"
syntax match   VerilogComment       "//.*"

syntax region  VerilogString        start=+"+ skip=+\\"+ end=+"+

" Modify the following as needed.  The trade-off is performance versus functionality.
syntax sync minlines=100

" highlight settings
highlight VerilogReservedWords   ctermfg=blue         guifg=blue
highlight VerilogSystemTasks     ctermfg=darkmagenta  guifg=darkmagenta
highlight VerilogBlockSentence   ctermfg=darkgrey     guifg=darkgrey
highlight VerilogPrecompile      ctermfg=lightblue    guifg=#0080C0
highlight VerilogDataType        ctermfg=darkgreen    guifg=darkgreen
highlight VerilogProcedure       ctermfg=yellow       guifg=#808000
highlight VerilogArithSynbol     ctermfg=brown        guifg=brown
highlight VerilogOperator        ctermfg=brown        guifg=brown
highlight VerilogSymbol          ctermfg=darkblue     guifg=darkblue
highlight VerilogNumber          ctermfg=lightred     guifg=#FF0080
highlight VerilogTimeScale       ctermfg=lightred     guifg=#FF0080
highlight VerilogComment         ctermfg=darkcyan     guifg=darkcyan
highlight VerilogString          ctermfg=magenta      guifg=magenta

let b:current_syntax = "verilog"

" vim: ts=8
